Directory-based cache coherence protocol for power-aware chip-multiprocessors.
Rana E. AhmedMuhammad K. DhodhiPublished in: CCECE (2011)
Keyphrases
- multithreading
- ibm power processor
- chip design
- high speed
- computational power
- power consumption
- parallel computing
- communication protocol
- highly efficient
- lightweight
- low cost
- high density
- security protocols
- shared memory
- metadata
- formal analysis
- physical design
- cryptographic protocols
- analog vlsi
- parallel implementation
- security analysis
- authentication protocol
- hierarchical structure