A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect.

Yoichiro Kurita Koji Soejima Katsumi Kikuchi Masatake Takahashi Masamoto Tago Masahiro Koike Koujirou Shibuya Shintaro Yamamichi Masaya Kawano

Published in: IEICE Trans. Electron. (2009)

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