A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON.

Quan Le Sang-Gug Lee Ho-Yong Kang Sang-Hoon Chang

Published in: ISSCC (2007)

Keyphrases

high speed
circuit design
low cost
post processing
power consumption
neural network
preprocessing step
high bandwidth
data mining
information retrieval
genetic algorithm
highly efficient
vlsi circuits