A 6.8GHz low-power and low-phase-noise phase-locked loop design.
Zhongtao FuJohn LeeAlyssa B. ApselPublished in: ISCAS (2008)
Keyphrases
- low power
- low power consumption
- high speed
- power consumption
- single chip
- low cost
- logic circuits
- vlsi architecture
- power dissipation
- phase locked loop
- mixed signal
- digital signal processing
- cmos technology
- image sensor
- high power
- power reduction
- nm technology
- gate array
- power saving
- design methodology
- design process
- ultra low power
- real time