Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs.

Andrzej Krasniewski

Published in: DSD (2008)

Keyphrases

error detection
error correction
embedded systems
dynamically created
error recovery
fault tolerance
error correcting
peer to peer
fault isolation
network structure
data transfer
error resilient
memory requirements
network bandwidth
smart camera
fault tolerant
wireless sensor networks