Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures.
Venkata Yaswanth RapartiSudeep PasrichaPublished in: ISQED (2016)
Keyphrases
- heterogeneous computing
- data transfer
- high speed
- compute intensive
- memory hierarchy
- memory management
- memory size
- low latency
- response time
- random access
- limited memory
- memory requirements
- main memory
- digital signal processors
- memory space
- analog circuits
- prefetching
- digital circuits
- computing power
- power dissipation
- memory usage
- design space exploration
- memory bandwidth