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A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.
Payam Ghafari
Ehsan Mirhadi
Mohab Anis
Shawki Areibi
Mohamed I. Elmasry
Published in:
IWSOC (2005)
Keyphrases
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low power
power consumption
high speed
low cost
single chip
wireless transmission
vlsi architecture
high power
cmos technology
gate array
vlsi circuits
digital signal processing
real time
power reduction
power saving
logic circuits
low power consumption
image sensor
design methodology
wireless sensor networks