High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA.
Martin LanghammerSergey GribokGregg BaecklerPublished in: FPGA (2020)
Keyphrases
- high density
- systolic array
- hardware implementation
- magnetic tape
- parallel architecture
- data flow
- linear array
- xilinx virtex
- low density
- field programmable gate array
- fpga device
- processing elements
- signal processing
- high power
- hardware architecture
- data center
- software implementation
- close proximity
- efficient implementation
- image processing algorithms
- floating point
- parallel processing
- high speed
- fpga implementation
- high bandwidth
- thin film
- low cost
- dedicated hardware
- hardware design
- verilog hdl
- magnetic recording
- real time image processing
- data mining
- fpga technology