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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources.
Zhiliang Qian
Ying Fei Teh
Chi-Ying Tsui
Published in:
VLSI-SoC (2011)
Keyphrases
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fault tolerant
fault tolerance
interconnection networks
distributed systems
dynamic reconfiguration
load balancing
routing algorithm
network on chip
metadata
shortest path
design process
case study
database systems
query processing
software architecture
design methodology