A low power reconfigurable accelerator using a back-gate bias control technique.
Hongliang SuWeihan WangKuniaki KitamoriHideharu AmanoPublished in: FPT (2013)
Keyphrases
- low power
- low cost
- cmos technology
- power consumption
- high speed
- power reduction
- nm technology
- single chip
- high power
- hardware and software
- vlsi architecture
- vlsi circuits
- low power consumption
- wireless transmission
- general purpose
- logic circuits
- image sensor
- real time
- field programmable gate array
- digital signal processing
- energy consumption
- signal processor