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A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM.
Takashi Sato
Yoji Nishio
Toshio Sugano
Yoshinobu Nakagome
Published in:
IEEE J. Solid State Circuits (1999)
Keyphrases
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data transfer
data flow
data transmission
high density
file system
main memory
parallel computers