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A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer.

Jae-Woo ParkDongsuk KangInjae ParkMinsu ParkXuefan JinKyu-Dong HwangDae-Han KwonJung-Hoon Chun
Published in: A-SSCC (2021)
Keyphrases
  • computer simulation
  • multipath
  • high speed
  • case study
  • database interface
  • phase locked loop
  • multiresolution
  • human computer interaction
  • interface design
  • ultra wideband