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Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.
Toru Shimizu
Masami Nakajima
Masahiro Kainaga
Published in:
IEICE Trans. Electron. (2006)
Keyphrases
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massively parallel
processing elements
computer architecture
case study
parallel computing
high performance computing
fine grained
single chip
parallel computers
hardware implementation
hardware design
parallel architecture
parallel architectures
hardware architecture
memory management