Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators.
Jung Hwan HeoArash FayyaziAmirhossein EsmailiMassoud PedramPublished in: ISLPED (2022)
Keyphrases
- convolutional neural network
- power dissipation
- power consumption
- low power
- design methodology
- face detection
- power reduction
- cmos technology
- clock frequency
- chip design
- logic circuits
- digital signal processing
- nm technology
- response time
- data flow
- parallel computing
- neural network
- energy efficiency
- flip flops
- field programmable gate array
- finite state machines
- low cost
- face recognition