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An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications.
Seungnam Choi
Hwan-Seok Ku
Hyunwoo Son
Byungsub Kim
Hong-June Park
Jae-Yoon Sim
Published in:
IEEE J. Solid State Circuits (2018)
Keyphrases
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low power
power consumption
low cost
high speed
single chip
image sensor
high power
wireless transmission
logic circuits
vlsi architecture
vlsi circuits
analog to digital converter
real time
image processing
digital signal processing
low power consumption