Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory.
Lee BaughNaveen NeelakantamCraig B. ZillesPublished in: ISCA (2008)
Keyphrases
- speculative execution
- transactional memory
- memory subsystem
- blue gene
- massively parallel
- address space
- hardware design
- parallel architectures
- field programmable gate array
- real time
- commodity hardware
- ibm zenterprise
- computing systems
- hardware and software
- operating system
- graphics processing units
- parallel computers
- parallel execution
- parallel computing
- open source
- highly parallel
- memory management
- memory access