Reconfigurable Fault Tolerant Processor on a SRAM based FPGA.
Bhargav ShashidharaShrikant JadhavYoungsoo KimPublished in: EIT (2020)
Keyphrases
- fault tolerant
- digital signal
- systolic array
- power reduction
- fault tolerance
- low power
- field programmable gate array
- single chip
- power consumption
- hardware implementation
- xilinx virtex
- parallel architecture
- low cost
- distributed systems
- high speed
- fpga device
- gate array
- load balancing
- random access memory
- general purpose processors
- interconnection networks
- multithreading
- hardware architecture
- data transmission
- parallel computing
- state machine
- parallel processing
- error detection
- processing elements
- safety critical
- shared memory
- computing systems
- database systems