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A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS.
Young-Ju Kim
Sang-Hye Chung
Lee-Sup Kim
Published in:
CICC (2011)
Keyphrases
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high speed
power consumption
low power
duty cycle
data sets
multiscale
cost function
computer simulation
constraint satisfaction
floating point
power dissipation