High-speed position detector using new row-parallel architecture for fast collision prevention system.

Yusuke Oike Makoto Ikeda Kunihiro Asada

Published in: ISCAS (4) (2003)

Keyphrases

parallel architecture
high speed
parallel processing
hardware implementation
systolic array
shared memory
low power
high level synthesis
distributed memory
frame rate
synthetic aperture sonar
real time
computer vision
parallel implementation
parallel algorithm
special case
high resolution
neural network