Noise Immunity Investigation of Low Power Design Schemes.
Mohamed AbbasMakoto IkedaKunihiro AsadaPublished in: IEICE Trans. Electron. (2006)
Keyphrases
- low power
- single chip
- power consumption
- low power consumption
- low cost
- high speed
- vlsi architecture
- logic circuits
- cmos technology
- noise immunity
- digital signal processing
- gate array
- ultra low power
- design process
- power reduction
- real time
- power dissipation
- multiresolution
- feature vectors
- mixed signal
- pattern recognition
- computer vision