Specification and verification of time requirements with CCSL and Esterel.
Charles AndréFrédéric MalletPublished in: LCTES (2009)
Keyphrases
- circuit design
- formal verification
- asynchronous circuits
- model checking
- formal methods
- protocol specification
- data sets
- high level
- formal specification
- colored petri nets
- data model
- formal analysis
- real time systems
- requirements analysis
- real time
- functional verification
- reactive systems
- machine learning
- communication protocols
- genetic algorithm
- requirements engineering
- learning environment
- business rules
- application specific