A 670 ps, 64 bit dynamic low-power adder design.
Ramchan WooSe-Joong LeeHoi-Jun YooPublished in: ISCAS (2000)
Keyphrases
- low power
- logic circuits
- power dissipation
- single chip
- power consumption
- low cost
- vlsi architecture
- low power consumption
- high speed
- cmos technology
- digital signal processing
- gate array
- vlsi circuits
- mixed signal
- nm technology
- analog to digital converter
- ultra low power
- real time
- power reduction
- design considerations
- delay insensitive
- design methodology
- data flow
- efficient implementation
- design process
- general purpose