Clock skew reduction in ASIC logic design: a methodology for clock tree management.
Alessandro BalboniClaudio CostiMassimo PellencinAndrea QuadriniDonatella SciutoPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
- design methodology
- high speed
- design process
- conceptual framework
- information systems
- design considerations
- duty cycle
- reference architecture
- single chip
- multi valued
- data management
- case study
- power consumption
- tree structure
- index structure
- classical logic
- user interface
- physical design
- hardware architecture
- data structure
- fpga device