A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.

Heiner Giefers Marco Platzner

Published in: FPL (2010)

Keyphrases

interconnection networks
routing algorithm
network on chip
low cost
high speed
fault tolerant
multistage
message passing
shortest path
multi processor
general purpose
wireless sensor networks
parallel algorithm
hardware implementation
program execution
reconfigurable architecture