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A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing.
Mu-Chen Huang
Shen-Iuan Liu
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2010)
Keyphrases
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power consumption
power allocation
analog to digital converter
case study
control system
motion estimation
digital images
high order
data flow
highly scalable