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A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture.
Hideo Yamasaki
Tadashi Shibata
Published in:
IEEE J. Solid State Circuits (2007)
Keyphrases
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image feature extraction
real time
vlsi architecture
shift register
high speed
vlsi implementation
image processing
hardware implementation
feature extraction
signal processing
image indexing
low cost
multiscale
co occurrence
image content
random number generator