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A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand".
Takanori Saeki
Masafumi Mitsuishi
Hiroaki Iwaki
Mitsuaki Tagishi
Published in:
IEEE J. Solid State Circuits (2000)
Keyphrases
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high speed
power consumption
duty cycle
decision trees
genetic algorithm
information systems
e learning
multi agent
lower bound