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Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line.
Sanghyeon Baeg
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2008)
Keyphrases
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low power
single chip
high speed
logic circuits
power consumption
vlsi architecture
low cost
digital signal processing
low power consumption
gate array
ultra low power
cmos technology
power reduction
high power
design methodology
mixed signal
vlsi circuits
fine grained
real time