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A low-overhead scheme for testing a bit-level finite ring systolic array.

Graham A. JullienSubir BandyopadhyayWilliam C. MillerMajid Taheri
Published in: J. VLSI Signal Process. (1990)
Keyphrases
  • low overhead
  • systolic array
  • parallel architecture
  • reconfigurable architecture
  • load balancing
  • shared memory
  • high reliability
  • data flow
  • graph cuts
  • scheduling algorithm