Bug Identification of a Real Chip Design by Symbolic Model Checking.

Ben Chen Michihiro Yamazaki Masahiro Fujita

Published in: EDAC-ETC-EUROASIC (1994)

Keyphrases

symbolic model checking
chip design
formal verification
model checking
partial observability
software engineering
source code
binary decision diagrams
data mining
image processing
signal processing
power consumption
symbolic representation
physical design
model checker