9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS.
Mitsuya FukazawaTakashi OshimaMasaki FujiwaraKatsuki TateyamaAlsubaie RaedMasao ItoTetsuya MatsumotoTetsuo MatsuiPublished in: ISSCC (2020)
Keyphrases
- cmos technology
- nm technology
- low power
- high speed
- power consumption
- low voltage
- power dissipation
- silicon on insulator
- parallel processing
- learning management systems
- circuit design
- single chip
- ct images
- metal oxide semiconductor
- mixed signal
- delay insensitive
- computed tomography
- e learning
- low cost
- camera parameters
- x ray
- medical images
- camera calibration
- analog vlsi
- cmos image sensor
- online learning
- analog to digital converter