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A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect.
Jun Pan
Yasuaki Inoue
Zheng Liang
Zhangcai Huang
Weilun Huang
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2007)
Keyphrases
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low power
low voltage
cmos technology
power consumption
low cost
high speed
mixed signal
power management
power line
single chip
design considerations
leakage current
digital signal processing
logic circuits
vlsi circuits
power reduction
vlsi architecture
power dissipation
real time
data center