Low power architecture for high speed packet classification.
Alan KennedyXiaojun WangZhen LiuBin LiuPublished in: ANCS (2008)
Keyphrases
- low power
- high speed
- vlsi architecture
- low cost
- power consumption
- single chip
- real time
- mixed signal
- high power
- cmos technology
- content addressable memory
- pattern recognition
- digital signal processing
- wireless transmission
- low power consumption
- vlsi circuits
- nm technology
- frame rate
- signal processor
- logic circuits
- image sensor
- design considerations
- image processing