A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS.
Joon-Yeong LeeJaehyeok YangJong-Hyeok YoonSoon-Won KwonHyosup WonJinho HanHyeon-Min BaePublished in: IEEE Trans. Very Large Scale Integr. Syst. (2016)
Keyphrases
- high speed
- cmos technology
- parallel processing
- low power
- parallel implementation
- low cost
- training phase
- massively parallel
- image processing
- silicon on insulator
- nm technology
- circuit design
- parallel programming
- learning phase
- power consumption
- computer architecture
- shared memory
- power supply
- computer simulation
- analog vlsi
- high resolution
- neural network
- ultra low power