A Concept for Test and Reconfiguration of a Fault-Tolerant VLSI Processor System.

Karl-Erwin Großpietsch Jörg Kaiser Edgar Nett

Published in: ISCA (1980)

Keyphrases

fault tolerant
fault tolerance
distributed systems
high speed
single chip
load balancing
state machine
fault isolation
signal processing
high availability
response time
chip design
vlsi design
gate array
database
safety critical
error detection
low power
data management