Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOS.
Song HuWeinan LiYumei HuangZhiliang HongPublished in: ASICON (2011)
Keyphrases
- low power
- low power consumption
- power consumption
- single chip
- high speed
- low cost
- cmos technology
- vlsi architecture
- logic circuits
- ultra low power
- mixed signal
- power dissipation
- vlsi circuits
- gate array
- digital signal processing
- cmos image sensor
- image sensor
- power reduction
- nm technology
- duty cycle
- real time
- delay insensitive
- design methodology
- analog to digital converter