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Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates.
G. Naveen Balaji
S. Chenthur Pandian
Published in:
Clust. Comput. (2019)
Keyphrases
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logic circuits
low power
circuit design
high speed
design process
power consumption
real time
single chip
gate array