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Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting.
Hao Ding
Junyan Qian
Bisheng Huang
Lingzhong Zhao
Zhongyi Zhai
Published in:
J. Parallel Distributed Comput. (2021)
Keyphrases
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mesh connected
processor array
array processor
massively parallel
rows and columns
data matrix
binary images
binary matrix
signal processing
parallel algorithm
image processing tasks
vlsi implementation
binary matrices
image processing
co occurrence
lot sizing