Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs.
Thomas B. PreußerPublished in: FPL (2017)
Keyphrases
- field programmable gate array
- hardware implementation
- data compression
- pipelined architecture
- fpga implementation
- parallel computing
- high speed
- parallel processing
- hardware software
- lightweight
- hardware and software
- processing elements
- massively parallel
- shared memory
- domain specific
- high level
- compression scheme
- data sets
- compression algorithm
- parallel implementation
- image processing algorithms
- singular value decomposition
- pattern matching
- image compression
- low cost
- general purpose