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Built-in jitter measurement circuit for PLL based on variable vernier delay line.

Zhikuang CaiHaobo XuShanwen HuJun Yang
Published in: IEICE Electron. Express (2017)
Keyphrases
  • high speed
  • digital circuits
  • electronic circuits
  • packet loss
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  • machine learning
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  • circuit design
  • analog circuits
  • power reduction