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Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.
Hsin-Chyh Hsu
Ming-Dou Ker
Published in:
ISQED (2006)
Keyphrases
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cmos technology
low power
spl times
power consumption
parallel processing
low voltage
low cost
high speed
image sensor
case study
pattern recognition
mixed signal