A Reconfigurable and Power-Scalable 10-12 Bit 0.4-44 MS/s Pipelined ADC With 0.35-0.5 pJ/Step in 1.2 V 90 nm Digital CMOS.
Mohammad Taherzadeh-SaniAnas A. HamouiPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)
Keyphrases
- analog to digital converter
- power consumption
- low power
- power reduction
- mixed signal
- low cost
- metal oxide semiconductor
- silicon on insulator
- cmos technology
- image sensor
- nm technology
- clock gating
- cmos image sensor
- circuit design
- general purpose
- data flow
- hardware implementation
- post processing
- power dissipation
- linear array
- dynamic range
- random access memory
- power saving
- pac man
- video sequences
- power management