Sign in
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Kwanseo Park
Woo-Rham Bae
Haram Ju
Jinhyung Lee
Gyu-Seob Jeong
Yoonsoo Kim
Deog-Kyoon Jeong
Published in:
ISCAS (2015)
Keyphrases
</>
high speed
power consumption
low power
cmos technology
nm technology
metal oxide semiconductor
circuit design
information systems
low cost
power management
hybrid learning
vlsi circuits
analog vlsi
low voltage
database
e learning
data sets
real time