A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications.
Seungjun BaekHyunjin AhnIlku NamJoonhoi HurYoungchang YoonOckgoo LeePublished in: IEICE Electron. Express (2018)
Keyphrases
- power consumption
- high power
- low power
- power supply
- high speed
- clock frequency
- cmos technology
- floating gate
- power management
- circuit design
- low cost
- parallel processing
- high density
- power dissipation
- wireless networks
- image sensor
- digital signal processing
- parallel implementation
- power reduction
- wireless local area network