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Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints.
Preetham Lakshmikanthan
Sriram Govindarajan
Vinoo Srinivasan
Ranga Vemuri
Published in:
IPDPS Workshops (2000)
Keyphrases
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high speed
low latency
human behavior
hardware implementation
load balance
signal processing
constraint satisfaction
constraint programming
constrained optimization
program synthesis
heterogeneous computing