A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation.
Man GuoM. Omair AhmadM. N. S. SwamyChunyan WangPublished in: ISCAS (2) (2003)
Keyphrases
- low power
- fpga implementation
- systolic array
- hardware implementation
- power consumption
- low cost
- high speed
- parallel architecture
- single chip
- data flow
- vlsi architecture
- real time
- field programmable gate array
- vlsi circuits
- low power consumption
- logic circuits
- signal processing
- hidden markov models
- cmos technology
- power dissipation
- image processing algorithms
- mixed signal
- low density parity check
- gate array
- noisy channel
- power reduction
- digital circuits
- image enhancement