12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Michael ClintonHank ChengHung-Jen LiaoRobin LeeChing-Wei WuJohnny YangHau-Tai HsiehFrank WuJung-Ping YangAtul KatochArun AchyuthanDonald MikanBryan SheffieldJonathan ChangPublished in: ISSCC (2017)
Keyphrases
- low power
- mobile applications
- cmos technology
- embedded dram
- power consumption
- nm technology
- signal processor
- vlsi architecture
- high speed
- low power consumption
- low cost
- mobile devices
- mobile phone
- context aware
- mixed signal
- user experience
- low voltage
- single chip
- power reduction
- mobile users
- smart phones
- power management
- logic circuits
- dynamic random access memory
- digital signal processing
- real time
- image sensor
- random access memory
- power dissipation
- design considerations
- vlsi circuits
- signal processing
- end users
- user interface