Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections.

Keitaro Koga Hiromitsu Awano Makoto Ikeda

Published in: ATS (2017)

Keyphrases

high speed
analog vlsi
circuit design
low power
chip design
image enhancement
power dissipation
random access memory
cmos technology
real time
image processing
coarse to fine
shift register
focal plane
built in self test
power reduction
programmable logic
vlsi implementation
genetic algorithm