Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects.

Kehan Zhu Sakkarapani Balagopal Vishal Saxena Wan Kuang

Published in: MWSCAS (2013)

Keyphrases

high speed
building blocks
design process
case study
computer aided
engineering design
cmos technology
neural network
user interface
wireless sensor networks
design methodology