Rule-based VLSI Verification System Constrained by Layout Parasitics.

Jacques Wenin Johan Verhasselt Marc Van Camp Jean Leonard Pierre Guebels

Published in: DAC (1989)

Keyphrases

expert systems
data driven
simulation software
signal processing
model checking
rule based systems
face verification
vlsi circuits
verification method
vlsi design
signature verification
formal verification
formal analysis
high speed
knowledge representation
layout design
concurrent systems
database